AMD to demo Quad Core Chips in Mid- 2006

[zippyjuan]

http://www.xbitlabs.com/news/cpu/display/20060126111118.html

AMD to Demo Quad-Core Chips in Mid-2006 [UPDATED].
AMD’s Quad-Core Processors to Show Up Soon

Category: CPU

by Anton Shilov

[ 01/26/2006 | 11:12 AM ]


UPDATE: Adding resolution to quad-core compatibility information, rewriting some text. Apparently, AMD's quad-core chips will only work on Socket F platform, not currently shipping. The representative by AMD wanted to say that the Socket F - initially dual-core platform - would support quad-core chips as well.

Advanced Micro Devices’ quad-core processors will be demonstrated as early as in the middle of this year and, perhaps, will be unveiled even earlier than expected according to some analysts. The forthcoming chips with four processing engines will be demonstrated on the next-generaion AMD server platforms that will ship this year.

“To go from single-core to dual-core to quad-core on the same platform, that has never been done in the industry,” said Marty Seyer, a senior vice president of AMD, reports InformationWeek web-site.

AMD plans to unveil server processors with virtualization technology and faster DDR2 memory support in mid-2006 and also to demonstrate its quad-core microprocessors in the same timeframe, the company is reported to have announced. The demonstrations will be carried out on the newly available server platforms for AMD Opteron processors, according to the web-site.

“When AMD rolls out dual-core processors with built-in virtualization hooks midyear, the company also aims to demo quad-core processors running on its current server platform,” Mr. Seyer is reported to have said.

It is expected that AMD’s dual-core processors with new memory controller and virtualization capabilities as well as quad-core processors will use a different socket and will sport DDR2 memory, two fundamentally different things from the current server platform by AMD.

AMD’s quad-core processors are due out in early 2007, but some industry analysts have said AMD could release them by the end of this year.

[LPMiller]

oh snap, I ran out of drool.

[zero2dash]

Did Socket M get rebadged as Socket F? (Or will there be both and F>M?)

In any event...*hooooooleeeeee crap* :eek: :drool:

[shocky123]

Socket M (maybe I'm thinking M2.. cannot remember if thats the same)
..but from what I'd heard is Socket M was a 940 chipset.. (same as the opteron line)

And from what I've read about Socket F, and their future sockets.. those are like 1072 pin chipsets.


granted, I could be wrong here...

~Kyle

[zippyjuan]

1207 pins for socket F. Socket M will be 940 from what I read.

[ShawnLee]

Dude. The idea of a quad core chip is just mind-boggling. Dude!

[bachviet]

Can't wait to get a dual-core after the quad-core comes out. :D

[Grimm]

oh snap, I ran out of drool.
:stupid:

I need a new keyboard. Mine just got soaked.

[hapoo]

I have a feeling that i'm going to look back on this the way i look back at ram. Back in my day, we didn't have 1 gigabyte of ram, we had 64K, and a 5 meg hard drive if we were lucky. --> Back in my day, we didn't have 128 cores, we were lucky to have one, and if that went bad, well we were SOL.

[pain2010]

:stupid:

[shocky123]

yeah hehehe.
I cant wait to be old an be able to say something like that.

no wait.

I can wait, in fact, I'll play with all these new upcoming toys until then.
heh

~Kyle

[shocky123]

Since I havent heard it from anywhere else yet.. does anyone have the inside scoop on the architecture of this chip??

I do high-performance-computing research, and have already found memory bandwidth problems on mutli-opteron boxes.
The problem occurs when memory which is 'local' to cpu-A is accessed from cpu-B. The access is handled over the HyperTransport layer, and so more and more traffic occurs over the HT bus as you scale up the number of cpus/cores.
Granted, this has only been observed on an 8-way opteron (8x single-core) setup.. I can easily envision a HUGE bottleneck occuring when you add 3 more cores into each processor. You would then have 4 cores competing for access to the single (1) onboard memory controller.

Now enough of the technical jargon.. (sorry guys)

So the question is......
Has anyone heard of any redesign (other than the DDR2 support) of the memory system on these chips?

~Kyle

[Grimm]

Granted, this has only been observed on an 8-way opteron (8x single-core) setup.. I can easily envision a HUGE bottleneck occuring when you add 3 more cores into each processor. You would then have 4 cores competing for access to the single (1) onboard memory controller.
The memory controller on the new Athlon 64s is intergrated into the CPU, shouldn't that alleviate some of the problems?

[Markel]

One of our customers was doing some prototyping for a CPU socket that had something like 1760 pins. I wonder what processor that will be for?

[shocky123]

The memory controller on the new Athlon 64s is intergrated into the CPU, shouldn't that alleviate some of the problems?

The problem I'm experiencing is on opteron systems with integrated memory controllers.

What I was alluding to is the potential problem when 4 cores share the same memory controller.

~Kyle